There exists a need to reliably interconnect very high density leadless circuit packages to circuit carrying substrates. Conventional design chip carriers employ solder joints on the peripheral edges of the leadless circuit package to interconnect to the circuit carrying substrate. This method produces large solder joints that are difficult to dimensionally control, due to variations in the amount of solder deposited, variations in the amount of solderable surface area and variations in the quality of the solderable surfaces. In addition, these types of leadless circuit packages are not amendable to very high density interconnection, due to constraints in the physical size of the solder joint needed and the lack of useable area on the perimeter of the carrier.
Very high density interconnect schemes employ an array of solderable pads on the underside of the leadless circuit package. This type of carrier is capable of significant higher density interconnections, and is known as a pad array chip carrier. Interconnecting these carriers to circuit carrying substrates is a difficult process, requiring very strict control of the dimensional tolerances of the components and the many processing variables in the soldering operaton.
One solution to this problem is to provide a fixed amount of solder on the pads of the pad array chip carrier prior to reflow to the circuit carrying substrate. Referring to FIG. 1, a pad array chip carrier 100 contains a solderable pad 102 configured such that the cross-sectional area and shape corresponds approximately to the cross-sectional area and shape of a solder sphere 106. The solder sphere 106 is then placed on the pad 102 and reflowed using methods known to those in the art. When complete, the pad array chip carrier has an array of precisely defined solder spheres attached to each solderable pad. The pad array chip carrier assembly (100 and 106) is placed on the circuit carrying substrate 110 and oriented such that the soldered sphere is aligned to and touching solderable pad 108 (FIG. 1B). The assembly is reflow soldered a second time to solder the pad array chip assembly to the circuit carrying substrate (FIG. 1C).
During the soldering operation, the distance between the pad array chip carrier and the circuit carrying substrate is typically reduced by 35-40%. This distance reduction is referred to as "collapse". Dimensional variations (camber) in the circuit carrying substrate and the pad array chip carrier cause the initial distance between the pad array chip carrier and the circuit carrying substrate to be non-uniform. This non-uniformity prevents some of the solder spheres from contacting the circuit carrying substrate. The collapse is not large enough to insure that every one of the spheres are soldered to the circuit carrying substrate, and some interconnections are not formed. In a typical pad array chip carrier, at least 64 and as many as 256 interconnections may be needed, and failure of only one interconnect constitutes failure of the entire device. The dimensional variations serve to impose an upper limit on the physical size of the pad array chip carrier that may be reliably interconnected. Using materials meeting industry standards of quality, pad array chip carriers no greater than 0.7 inch .times.0.7 inch can be used, thus limiting the maximum number of interconnections to less than 100.
Mismatches in the thermal co-efficient of expansion between the pad array chip carrier and the circuit carrying substrate impose large stresses on the assembled package during thermal excursions. To minimize these stresses, larger solder pad areas are employed in certain areas, such the corners of the device, to reduce the amount of stress. The use of large solder pads on the underside of the pad array chip carrier reduces the height of the resultant solder sphere, thus reducing the amount of collapse during reflow to the circuit carrying substrate. A typical situation is a collapse of only 20%. This attempt to reduce solder joint stress results in a reduction in the collapse, and thus a reduction in the amount of allowable tolerances, and non-uniformity between the two components, a reduction in the size of a pad array chip carrier that can be used, and an increase in the number of unsoldered connections. The amount of collapse may be restored by comparably increasing the size of the solder sphere, However, this solution is only applicable to those cases where all the pads are of uniform size, and results in significantly decreased interconnection density. If it is desired to effect larger pads in selected areas only, such as corners of the pad array chip carrier, multiple sizes of solder spheres must be employed in order to achieve a uniform height of spheres on the underside to the pad array chip carrier prior to attachment to the circuit carrying substrate. In practice, this solution is difficult to achieve, and requires a significant increase in the complexity and amount of tooling necessary to precisely place solder spheres of multiple diameter on the same pad array chip carrier.
Clearly, a need exists to achieve increased collapse distance and to accommodate the use of pads of mixed sizes within a single pad array chip carrier.